(1) Field of the Invention
The invention relates to semiconductor memory devices, and, more particularly, to a method of forming a split gate flash memory with minimal floating gate-to-floating gate spacing.
(2) Description of the Prior Art
A split gate flash memory device is essentially a MOS transistor with a variable threshold voltage. The threshold voltage varies with the amount of charge that is stored on a floating gate structure. The floating gate structure overlies a first part of the device channel region. A control gate structure overlies a second part of the device channel region. Voltage on the control gate controls the second part of the device channel region directly and controls the first part of the device channel indirectly, as modulated by charge on the floating gate. The control gate is formed in close proximity to the floating gate so that a capacitive coupling between the control gate and the floating gate is achieved.
Flash memories have undergone significant improvements over the years. In particular, device size has been dramatically reduced. Further reductions in the device size require technological innovations. In particular, the spacing between the floating gates of adjacent split gate flash cells is a significant problem. Currently, the floating gates are patterned, or defined, using a lithographic system. For example, after the deposition of a floating gate layer, the semiconductor wafer is then coated with a photoresist layer. The photoresist layer is exposed to actinic light through a mask. After development, a pattern of photoresist is left on the wafer overlying the floating gate layer. The floating gate layer is then etched where exposed by the patterned photoresist layer.
There are several difficulties in minimizing the cell-to-cell spacing of the split gate flash cells. The floating gate spacing is often the limiting factor in the cell-to-cell spacing. If the floating gate spacing is made too small, then misalignment in the lithography process or variation in the etching process may lead to bridging or shorting of the floating gates. Alternatively, increasing the floating gate spacing will cause the floating gate overlap of active area (OD) to decrease. Misalignment or overetching could then cause the active area to be uncovered by the floating gate edge. This would result in leaky devices. Finally, methods to self-align the floating gate to the active area result in overly complicated processes or in residue issues. A primary goal of the present invention is to provide a method to reduce cell-to-cell spacing without reducing reliability or yield and without significant complexity.
Several prior art inventions relate to flash memory cells. U.S. Pat. No. 5,915,178 to Chiang et al, U.S. Pat. No. 6,380,583 B1 to Hsieh et al, U.S. Pat. No. 6,403,494 B1 to Chu et al, and U.S. Pat. No. 6,326,660 B1 to Lin et al teach methods to form split gate flash memories. An oxide layer is formed overlying a polysilicon layer. This oxide layer is used as a hard mask for etching the polysilicon layer to form floating gates. However, the oxide hard mask dimensions are the same as those of the silicon nitride opening. U.S. Pat. No. 5,643,814 to Chung describes a method of making a split gate flash memory.